1. Field
The field of the present invention relates to particle beam lithography, and in particular to stencil design and a method for cell projection particle beam lithography.
2. Description of Related Art
In current semiconductor manufacturing processes, optical lithography with photomasks is commonly used. Photomasks consist of a glass substrate and mask patterns drawn on it and are commonly used to form device patterns on a silicon wafer. However, as the feature size becomes smaller than the wavelength of the ultraviolet light, which is used to optically transcribe mask patterns onto a silicon wafer, optical proximity effect becomes significant and accurate transcription becomes difficult.
To correct this effect an Optical Proximity Correction (OPC) technique is used, which often requires costly computation time and electron beam (EB) writing time, resulting in a low manufacturing yield. To solve this mask cost issue, various approaches such as maskless lithography (ML2), which does not use a photomask, have been proposed. One of the promising approaches among various ML2 techniques includes electron beam direct writing (EBDW) and has been practically used by some semiconductor manufacturers.
Referring to FIG. 1, a conventional particle beam writer, such as an electron beam (EB) writer, with cell projection (CP) capability provides for a cell projection particle beam write, such as a cell projection electron beam write. As shown, a particle or electron beam source 100 provides a particle or electron beam 102 to a first mask 112 that can be formed to a rectangular shape 114 with a first aperture 110 formed in the first mask 112. The rectangular beam 114 is then directed to a second mask 122 and through a second aperture 120 formed in the second mask 122. The second mask 122 is configured for EB lithography and includes apertures 120 that define various types of cell patterns.
Each cell pattern of the second mask 122 is indicative of various types of electronic circuit blocks, such as inverters, flip flops and memory blocks. For example, the electron beam 102 is shaped into the rectangular pattern of the first aperture 110, and then a complex cell pattern 124, such as an inverter, may be formed by electron beam projection through the second aperture 120 of the stencil mask 122.
In general, a variable shape beam (VSB) machine (not shown) would only have simple patterns in a second aperture, which result in simple shapes, such as rectangular or triangular shapes with variable sizes for projection on a wafer or substrate. A chip pattern may be drawn with these simple rectangular or triangular shapes. In the case of CP (cell projection), as shown in FIG. 1, the second aperture or stencil mask 22 may contain a plurality of cell patterns, such as about 100 cell patterns. Each cell pattern may comprise complex patterns on the scale of 10×10 um2 in size. Such patterns on stencil masks may include patterns of standard cell library entities, such as an inverter or flip-flop.
Referring to FIG. 2, a typical layout of a cell area, or cell patterns, 142 is formed on a stencil mask 140. By selecting one of such cells, the pattern can be drawn on a wafer by one shot of EB exposure, in contrast to ten or more shots with the case of a VSB machine, which greatly reduces EB writing time.
The cell projection (CP) technique was proposed to reduce writing time of EB. The CP technique enables a cell pattern to be drawn by one shot and thus reduces overall writing time compared to a conventional variable shape beam (VSB) method. However, a problem with CP is the limitation of the number of cells that can be contained on one stencil mask, such as 100. Since a cell library of ASICs usually has 300 to 500 cells and the stencil mask should contain all the possible orientations of each cell resulting in approximately 1200 to 2000 patterns needed on a stencil mask, each and every cell pattern needed is not likely to be accommodated on a single stencil mask. The limited cell number on the stencil results in that only a part of cells used in an integrated circuit (IC) chip can be written with CP and the remaining part of the chip pattern must be drawn by conventional VSB, which results in a limited throughput improvement and hinders its use for volume production. This drawback has restricted practical usage to only small volume production chips, such as ASICs, or purely for research purposes.